The short channel behaviors of fin field effect transistors (FINFETs) are controlled by fin thickness due to the fully depleted nature of the devices. Short channel behaviors and fin thickness (Dfin) in FINFET devices are described, for example, in Chung-Hsun Lin et al., “Non-Planar Device Architecture for 15 nm Node: FinFET or Trigate?,” 2010 IEEE International SOI Conference (SOI), pgs. 1-2, Oct., 2010. Thus, control over fin thickness variations is important to achieve a viable technology.
Conventional approaches for quantifying fin thickness variation include top-down scanning electron micrograph (SEM) analysis or physical analysis of a transmission electron micrograph (TEM) cross-section cut. Unfortunately, both of these processes can be very time consuming and destroy the wafer.
Thus, efficient techniques for quantifying fin thickness variation in FINFET devices that do not damage the wafer would be desirable.